Research Line A
Micro/Nanoelectronics
Objectives

The main objective of the group for next years is:

  • Research and implementation of highly energy efficient and autonomous reconfigurable micro-systems by combining ultra-low power and low-cost innovative techniques in the design of adaptable integrated circuit building blocks for CMOS nanoscale technology.

The work developed in the period 2008-2012, will continue for the period 2013-2016 within the scope of the FCT Project DISRUPTIVE (EXCL/EEI-ELC/0261/2012). This project, which has been considered as a research line of excellence, in the 2012 FCT call, is associated with a five-year scientific plan (up to 2018); although the timeframe to the financial execution is limited to the period of three years.

This project´s objective is a global paradigm shift: analog and mixed-signal blocks will be based on passive devices (resistors, capacitors and inductors) and the transistors will be used only as nanoswitches, as variable capacitors (varactors), or as logic gates. This approach allows to avoid using transistors as amplifiers, which is undesirable because of the low intrinsic gain of transistors in deep nanometer technologies.

Major innovative techniques, will be developed:

  1. either continuous-time or discrete-time parametric amplification;
  2. switched-capacitor circuits operating in the ultra-incomplete-settling regime and using low gain amplifiers.

Research activities will also include:

  • Improved modeling to take into account the new effects due to downscaling of transistor dimensions;
  • Optimization envisaging design-for-manufacturing;
  • Methods to produce reliable circuits out of unreliable components;
  • Design of digitally assisted analog circuits for flexible and reconfigurable systems.

All the circuits and methodologies developed in project DISRUPTIVE will be within the scope the strategy of CTS-UNINOVA research Centre.

We will develop nanometer scale CMOS circuits covering the following areas:

  1. Analog to digital and digital to analog conversion and innovative low-power RF transceivers.
  2. RF key blocks of future reconfigurable transceivers (LNAs, multiphase oscillators, mixers, filters and frequency conversion circuits)
  3. Development of optimization algorithms and methodologies capable of dealing with the design issues associated with nanometer CMOS technologies.
  4. Development of energy efficient computing systems for system on chip (SoC) in advanced nanometer CMOS technologies.
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